OPERATOR GUIDE / TIME

Cycle delay

Move exactly N sampled cycles forward.

##N

Syntax at a glance

req |-> ##2 ack

How it works

A fixed cycle delay moves a sequence's next condition forward by exactly N sampled clock cycles. In req |-> ##2 ack, a request at cycle t requires ack at t+2. Count sample boundaries, not how long the waveform's drawn pulse looks. ##0 checks the current cycle.

For req = [0, 1, 0, 0, 0] and ack = [0, 0, 0, 1, 0], the request at cycle 1 is satisfied at cycle 3. An ack at cycle 2 alone is too early; an ack at cycle 4 alone is too late. Additional ack pulses are legal as long as the required one is present. This property does not mean ack may occur only at t+2.

Every high request sample creates an obligation. Adjacent requests at cycles 1 and 2 require acknowledgements at cycles 3 and 4. If you intend a single trigger when req rises, use $rose(req) as the antecedent instead.

Delays can be chained: req |-> ##1 ack ##1 !busy requires ack at t+1 and !busy at t+2 along the same sequence. Each later delay is measured from the preceding matched condition. With |=>, one cycle is already added before any explicit delay; req |=> ##1 ack checks t+2.

The lab accepts integer delays from 0 through 128. If a triggered obligation cannot finish before the trace ends, it fails and Studio reports the unresolved boundary. Pad authoring traces so reference obligations finish. Delay syntax is part of a sequence, not a Boolean operator.

Examples describe AssertionQuest's sampled, binary educational subset. Properties are evaluated at every cycle; enter only the property body in the editor.
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