01AVAILABLE100 XP
First Property
Whenever a is high, b must be high in that same cycle.
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FOUNDATION COURSE
SVA Fundamentals
Learn to express digital behavior, one carefully sampled cycle at a time.
0/12CHALLENGES COMPLETE
01
Logic & Implication
Start with the relationship between signals.
02AVAILABLE110 XP
Combining Conditions
Whenever req is high and busy is low, ack must be high in the same cycle.
02
Thinking in Time
Turn clock boundaries into precise obligations.
03AVAILABLE120 XP
One Cycle Later
For every sampled high req, ack must be high one cycle later.
04AVAILABLE140 XP
Exact Delay
For every sampled high req, ack must be high exactly two cycles later. Other ack pulses are allowed.
05AVAILABLE120 XP
Next-Cycle Implication
Whenever req is sampled high, ack must be high on the next cycle.
03
Signals Have a Memory
Reason about previous values, edges, and stability.
06AVAILABLE150 XP
Previous Value
At every cycle, b must equal the previous sampled value of a. Missing history is zero.
$past()Log in to begin →07AVAILABLE150 XP
Rising Edge
When start transitions from 0 to 1, pulse must be high in that cycle. Holding start high adds …
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Falling Edge
When start transitions from 1 to 0, pulse must be high in that cycle.
$fell()Log in to begin →09AVAILABLE170 XP
Stability
Whenever busy is high, data must equal its previous sampled value. busy is low at cycle zero.
$stable()Log in to begin →04
Timing Windows
Combine your tools to describe richer behavior.
10AVAILABLE180 XP
Response Window
After every sampled high req, ack must occur between one and three cycles later, inclusive.
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Edge-Triggered Response
After each rising edge of req, ack must occur one to three cycles later. A held request creates …
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The Final Handshake
When req is high and busy is low, one or two cycles later ack must be high and …