Read the timing.
Follow real digital waveforms. Find the relationship between signals and clock cycles.
THE INTERACTIVE VERIFICATION LAB
Every waveform
tells a story.
Learn to prove it.
Turn digital behavior into precise assertions. Solve waveform puzzles, test your reasoning, and build your SystemVerilog toolkit—one cycle at a time.
12 hands-on challengesReal behavioral gradingNo tools to install
LIVE CONCEPT / 004
clk ↑THE CHALLENGE
A request. A response.
Exactly two cycles apart.
assert property (@(posedge clk)
req |-> ##2 ack);✓
Intent, expressed precisely.Each request creates an obligation two cycles later.
Learn formal verification by proving what waveforms mean.
Write the property.
Translate the requirement into an assertion using a growing toolbox of SVA operators.
Challenge your logic.
Hidden traces test what you accept and reject. Learn why a property is too loose or too strict.
YOUR FIRST EXPEDITION
SVA Fundamentals
Logic & implication → Time → History → Timing windows